
ECE 4514: Digital Design IIThis is the course outline for =
the=20
Spring 2008 version of Digital Design II.=20
Instructor: Patrick =
Schaumont=20
Venue: TR 11:00AM12:15PM, Durham Hall 261
Syllabus=20

Lecture 1 
Introduction [Slides]=20
 Overview=20
 Motivation for the use of Hardware Description Languages=20

Lecture 2 
Hierarchical Design [Slides]=20
 Structural and Behavioral Modeling=20
 Topdown and Bottomup Design=20
 4bit counter example and simulation in Modelsim =

Lecture 3 
Verilog Bread and Butter [Slides]=20
 Verilog for Synthesis and Simulation=20
 Verilog Module Structure: Port List, =
Behavioral/Dataflow/Structural=20
constructs=20
 Verilog Data Types, Values and Constants =

Lecture 4 
Gate Level Modeling [Slides]=20
 Structural Modeling with gatelevel primitives=20
 Delay modeling at gate level=20
 Examples: Bit and Byte Comparator, Latches and Flip Flops=20

Lecture 5 
How the Verilog Simulator Works [Slides]=20
 Structure and operation of an eventdriven simulator=20
 Simulation of gate networks with an eventdriven simulator=20
 Simulation of behavioral code with an eventdriven simulator =

Lecture 6 
Random Number Generators [Slides]=20
 True RNG and Pseudo RNG=20
 Fibonacci and Galois LFSR=20
 Flaws in RNG: bias, predictability=20
 Nonlinear combination generators

Lecture 7 
Dataflow Modeling [Slides]=20
 Use of assign statement, formation of operands using =
bitselect and=20
partselect=20
 Delay in dataflow assignment=20
 Verilog operators, expressions, precision in expressions=20

Lecture 8 
Multiplexed Datapaths [Slides]=20
 Multiplexed datapaths can be made using registers and assign =
statements=20
 Rules: use singleclock, use edgetriggered flipflops, use=20
registerattheoutput=20
 Through multiplexed datapaths, we can tradeoff area and =
time for=20
different solutions=20
 Finite State Machines can be modeled using the same approach =

Lecture 9 
System Commands and Testbenches [Slides]=20
 System commands for display and file I/O=20
 VCD Files, format and usage

Lecture 10 
Behavioral Modeling: Nonblocking Assignments [Slides]=20
 Nonblocking assignments split RHS evaluation from LHS =
assignment=20
 Used to model registers in always blocks=20
 VCD Files

Lecture 11 
Design of a SHA1 Module in Verilog [Slides]=20
 SHA1 =3D Secure Hashing Algorithm=20
 Illustration of nonblocking assignment (<=3D) and=20
registertransfer level design

Lecture 12 
Behavioral Modeling/ Conditionals and Loops [Slides]=20
 Elements of Behavioral Modeling=20
 iftheelse, case=20
 loops=20
 parallel block, named block
 Generate statement

Lecture 13 
Logic Synthesis [Slides]=20
 Hardware Inference: The rules that govern Verilog to =
hardware=20
translation=20
 How to capture combinational logic in an always block=20
 How to capture registers in an always block=20
 How to recognize warnings and errors from the tools when you =
synthesize your design

Lecture 14 
Spartan 3ES500 FPGA [Slides]=20
 Implementation details of FPGA: CLB's and the =
interconnection=20
network=20
 Analysis of data sheet table, tool diagnostic output =

Lecture 15 
FSMbased Control [Slides]=20
 Verilog mapping for synthesizable FSM=20
 State encoding using synthesis tools=20
 Synthesis issues: default state assignment, safe FSM, =
RAMbased FSM=20
 FSMbased control of datapath

Lecture 16 
Synthesis of Memories in FPGA [Slides]=20
 Design flow for Memory Elements=20
 Inference and instantiation=20
 Integrated synthesis and simulation
 Memory Elements=20
 Register Files=20
 Memory Arrays: SRAM and DRAM=20
 Operation of SRAM and DRAM=20
 SRAM in Spartan 3E FPGA

Lecture 17 
Hardware Division [Slides]=20
 Division as an 'inverted' multiplication=20
 Division one digit atatime: digitrecurrence=20
 The restoring divider algorithm=20
 The nonrestoring divider algorithm=20
 Designing an architecture for a nonrestoring divider =

Lecture 18 
Optimizing Area [Slides]=20
 Area and Performance Constraints in digital design=20
 AreaDelay product and 'optimal' design=20
 Area optimization using resource sharing=20
 Hardware sharing factor=20
 Example: unshared multiplier, shared multiplier, =
multiplication with=20
a constant

Lecture 19 
Optimizing Performance [Slides]=20
 Performance factors of a digital design=20
 Latency and Throughput=20
 Delay =3D Clock Period * Cycle Count=20
 What determines the minimum clock period?=20
 Performance Optimizations you can do in Verilog=20
 Parallel Computations=20
 Pipelining=20
 Retiming
 Summary Optimizing Area & Performance =

Lecture 20 
Static Timing Analysis [Slides]=20
 Static and Dynamic Timing Analysis=20
 Static Timing Analysis=20
 Delay Model=20
 Path Delay=20
 False Paths=20
 Timing Constraints=20
 FPGA Design Flow & STA: Sorter Example
 Dynamic Timing Analysis=20
 FPGA Design Flow & Timed Simulation=20
 Delay backannotation with SDF files
 Demonstration

Lecture 21 
Functions and Tasks [Slides]=20
 Functions and Tasks=20
 Functions and Tasks enable shorthand notations within always =
and=20
initial blocks=20
 Functions are singleoutput, and do not support event =
control=20
 Tasks may have more then a single output, and may have =
eventcontrol=20
statements=20
 In practice, only functions are used in synthesis =

Lecture 22 
Design Economics [Slides]=20
 Wows and Woes of scaling=20
 The case of the Microprocessor=20
 How efficient does a microprocessor use transistors ? =
 Alternative Technologies: FPGA, ASIC, Full Custom=20
 Energy Efficiency and Design Cost
=20
